Using copper for interconnections for transistor source/drain and gate regions can present some design challenges. For example, copper that is formed within typical trench contacts should be well contained to avoid issues associated with what is known as array leakage. Array leakage occurs when the copper within the trench contact leaks into or extrudes into underlying substrate regions. This can and typically does compromise a device.
One way to contain the copper is to provide a barrier layer within the trench contact. Typically, a common approach is to form a relatively strong barrier having a metallurgical consistency that is the same along both the sidewalls and the bottom of the trench contact. This, however, is not the best approach as it can lead to compromise of the line and contact resistances. That is, in the interest of having a robust barrier to address array leakage, line and contact resistances can be compromised.